1. Technical Field
Various exemplary aspects of the present invention relate to a semiconductor apparatus. In particular, certain exemplary aspects relate to a three-dimensional semiconductor apparatus.
2. Related Art
In order to increase the degree of integration of a semiconductor apparatus, a 3D (three-dimensional) semiconductor apparatus has been developed. The 3-D semiconductor apparatus includes a plurality of chips stacked for placement in a single package. The resultant structure is then packaged. The 3D semiconductor apparatus may achieve a maximum degree of integration in the same space by vertically stacking two or more chips.
The 3D semiconductor apparatus may be realized in a variety of ways. For example, when a plurality of structurally similar chips are stacked and are connected to each other with metal wires, they can operate as a single semiconductor apparatus.
Recently, a TSV (through-silicon via) semiconductor apparatus has been disclosed in which silicon vias pass through a plurality of stacked chips so that all the chips are connected to each other. Since the through-silicon vias pass through the respective chips vertically in the TSV type semiconductor apparatus, the package size is much smaller compared to the semiconductor apparatus in which respective chips are connected through the wires.
In general, the TSV type semiconductor apparatus may be composed of a master chip and a plurality of slave chips which are connected to the master chip through TSVs. For example, in a memory apparatus, the master chip includes all logic circuits in a peripheral circuit region for the operation of the memory apparatus. The slave chips include memory cores in which data may be stored and circuits for the operation of the memory cores, so as to operate as a single semiconductor apparatus.
When a plurality of chips are stacked in the 3D semiconductor apparatus, they share data input and output since they operate as a single semiconductor apparatus. In a semiconductor apparatus containing wired connections, the data outputted from respective stacked chips may be transferred to a controller through input/output lines. In a semiconductor apparatus containing TSV connections, the slave chip data may be transmitted to the master chip and may be outputted through pads located on the master chip. In order to improve the operational speed of the semiconductor apparatus, the output timing of the data transmitted from the stacked chips need to substantially coincide.
Because the stacked chips have different characteristics due to variations in PVT (process, voltage and temperature), however, they can hardly show the same performance characteristics. More specifically, the respective chips have skews due to their different PVT properties. Thus, a skew may result from the difference in data output timing between a chip with a high operational speed and one with a low operational speed. Consequently, the operational speed of the semiconductor apparatus may be lowered when trying to secure a valid data window with the existence of the skew.